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CY7C374
UltraLogicTM 128-Macrocell Flash CPLD
Features
* * * * * * 128 macrocells in eight logic blocks 64 I/O pins 6 dedicated inputs including 4 clock pins Bus Hold capabilities on all I/Os and dedicated inputs No hidden delays High speed -- fMAX = 100 MHz -- tPD = 12 ns -- tS = 6 ns -- tCO = 7 ns * Electrically Alterable Flash technology * Available in 84-pin PLCC, 84-pin CLCC, 100-pin TQFP, and 84-pin PGA packages * Pin compatible with the CY7C373
Functional Description
The CY7C374 is a Flash erasable Complex Programmable Logic Device (CPLD) and is part of the FLASH370 family of high-density, high-speed CPLDs. Like all members of the FLASH370 family, the CY7C374 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. The 128 macrocells in the CY7C374 are divided between eight logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370 architecture are connected with an extremely fast and predictable routing resource--the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. The CY7C374 is a register intensive 128-Macrocell CPLD. Every two macrocells in the device feature an associated I/O pin, resulting in 64 I/O pins on the CY7C374. In addition, there are two dedicated inputs and four input/clock pins.
Logic Block Diagram
CLOCK INPUTS INPUTS
2 INPUT MACROCELLS 4 8 I/Os I/O0-I/O7 LOGIC BLOCK 36 16 36 16 36 16 36 16 PIM
4 INPUT/CLOCK MACROCELLS 4 36 16 36 16 36 16 36 16 LOGIC BLOCK 8 I/Os I/O56-I/O63
A
8 I/Os LOGIC BLOCK
H
LOGIC BLOCK 8 I/Os
I/O8-I/O15
B
8 I/Os LOGIC BLOCK
G
LOGIC BLOCK 8 I/Os
I/O48-I/O55
I/O16-I/O23
C
8 I/Os LOGIC BLOCK
F
LOGIC BLOCK 8 I/Os
I/O40-I/O47
I/O24-I/O31
D
E
32
I/O32-I/O39
7C374-1
Selection Guide
Maximum Propagation Delay tPD (ns) Minimum Set-Up, tS (ns) Maximum Clock to Output, tCO (ncs) Maximum Supply Current, ICC (mA)
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Cypress Semiconductor Corporation Document #: 38-03021 Rev. **
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7C374-100 12 6 7 Commercial Military/Industrial 300
7C374-83 15 8 8 300 370
7C374-66 20 10 10 300 370
7C374L-66 20 10 10 150
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 Revised April 1998
www..com
CY7C374
Pin Configurations
PGA Bottom View
L I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND I/O7 I/O6 I/O5 I/O4 I/O3 GND VCC I/O2 I/O1 I/O0 VCC I/O23 I/O25 I/O26 I/O28 I/O31 I/O33 VCC I/O34 I/O36 I/O37 I/O39
PLCC/CLCC Top View
I5
K
I/O21
GND
I/O24
I/O27
I/O30
I2
I/O32
I/O35
I/O38
GND
I/O41
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I 0 VCC GND CLK1/I 1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND 74 12 73 13 72 14 71 15 70 16 69 17 68 18 67 19 66 20 65 21 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I 4 GND VCC CLK2/I 3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 J I/O20 I/O22 I/O29 VCC GND I/O40 I/O42
H
I/O18 CLK1 / I1 I/O17
I/O19 I/O16 GND
I/O43
I/O44
G
CLK2 /I3 VCC
I/O46
I/O47
F
CLK0 /I0 I/O14
VCC
I/O45
GND
E
I/O15
I/O13
I/O49
I/O48
CLK3 /I4 I/O50
D
I/O12
I/O11
I/O51
C
I/O10
I/O8
I/O1
VCC
I5
I/O54
I/O52
B
I/O9
GND
I/O6
I/O3
I/O0
I/O61
I/O62
I/O59
I/O56
GND
I/O53
A
I/O7 1
I/O5 2
I/O4 3
I/O2 4
VCC 5
GND 6
I/O63 7
I/O60 8
I/O58 9
I/O57 10
I/O55 11 7C374-3
7C374-2
TQFP Top View
VCC GND NC VCC I5 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I0 VCC N/C GND CLK1/I1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC VCC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I4 GND NC VCC CLK2/I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 GND NC
7C374-4
NC GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 VCC
Document #: 38-03021 Rev. **
NC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC
NC
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CY7C374
Functional Description (continued)
Finally, the CY7C374 features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used or the type of application, the timing parameters on the CY7C374 remain the same. Logic Block The number and configuration of logic blocks distinguishes the members of the FLASH370 family. The CY7C374 includes eight logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. Product Term Array The product term array in the FLASH370 logic block receives 36 inputs from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows very complex functions to be implemented in a single pass through the device. Product Term Allocator The product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to increase the effective density of the FLASH370 CPLDs. Note that product term allocation is handled by software and is invisible to the user. I/O Macrocell Half of the macrocells on the CY7C374 have I/O pins associated with them. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The I/O macrocell includes a register that can be optionally bypassed, polarity control over the input sum-term, and two global clocks to trigger the register. The macrocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is to be used as an input. Buried Macrocell The buried macrocell is very similar to the I/O macrocell. Again, it includes a register that can be configured as combinatorial, as a D flip-flop, a T flip-flop, or a latch. The clock for this register has the same options as described for the I/O macrocell. One difference on the buried macrocell is the addition of input register capability. The user can program the buried macrocell to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the eight logic blocks on the CY7C374 to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. Bus Hold Capabilities on all I/Os and Dedicated Inputs A feature called bus-hold has been added to all FLASH370 I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. Development Tools Development software for the CY7C374 is available from Cypress's WarpTM software packages. Both of these products are based on IEEE standard 1076/1164 VHDL. Cypress CPLDs are also supports by a number of third-party vendors such as ABELTM CUPLTM, and LOG/iCTM. Please refer to third-party tool support data sheets for further information.
Document #: 38-03021 Rev. **
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CY7C374
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage to Ground Potential .................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................-0.5V to +7.0V DC Input Voltage .................................................-0.5V to +7.0V DC Program Voltage .....................................................12.5V Range Commercial Industrial Military
[1]
Output Current into Outputs ........................................ 16 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Ambient Temperature 0C to +70C -40C to +85C -55C to +125C VCC 5V 5% 5V 5% 5V 10%
Electrical Characteristics Over the Operating Range[2]
Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[4, 5] Power Supply Current[6] VCC = Min. VCC = Min. Test Conditions IOH = -3.2 mA (Com'l/Ind) IOH = -2.0 mA (Mil) IOL = 16 mA (Com'l/Ind) IOL = 12 mA (Mil) Guaranteed Input Logical HIGH voltage for all inputs[3] Guaranteed Input Logical LOW voltage for all inputs VI = Internal GND, VI = VCC Vo = Internal GND, Vo = VCC VCC = Max., VOUT = 0.5V VCC = Max., IOUT = 0 mA f = 1 MHz, VIN = GND, VCC Com'l Com'l "L" -66 Mil./Ind.
Shaded area contains preliminary information.
Min. 2.4
Max.
Unit V V
0.5 2.0 -0.5 -10 -50 -30 7.0 0.8 +10 +50 -160 300 150 370
V V V V A A mA mA mA mA
[3]
Capacitance[5]
Parameter CI/O
[7, 8]
Description Input Capacitance
Test Conditions VIN = 5.0V at f=1 MHz
Max. 10
Unit pF
Endurance Characteristics[5]
Parameter N Description Minimum Reprogramming Cycles Test Conditions Normal Programming Conditions
5. 6. 7. 8.
Min. 100
Max.
Unit Cycles
Notes: 1. TA is the "instant on" case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect these parameters. Measured with 16-bit counter programmed into each logic block. CI/O for the CLCC and CPGA packages is 15 pF max. CI/O for I5 is 15 pF max
Document #: 38-03021 Rev. **
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CY7C374
AC Test Loads and Waveforms
238 (COM'L) 319 (MIL) 5V OUTPUT 35 pF INCLUDING JIG AND SCOPE 170 (COM'L) 236 (MIL) 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 238 (COM'L) 319 (MIL) 3.0V 170 (COM'L) 10% GND 236 (MIL) 2 ns ALL INPUT PULSES 90% 90% 10%
2n
(a)
Equivalent to: TH EVENIN EQUIVALENT 99 (COM'L) 136 (MIL) 2.08V (COM'L) 2.13V (MIL)
(b)
7C374-5
7C374-6
OUTPUT
Parameter[9] tER(-)
VX 1.5V VOH
Output Waveform Measurement Level
-0.5V tER(+) 2.6V -0.5V VOH tEA(+) 1.5V -0.5V VX tEA(-) Vthc VX -0.5V
Note: 9. tER is measured with 5-pF AC Test Load and tEA is measured with 35-pF AC Test Load.
VX
VX
VOH
VOH
Document #: 38-03021 Rev. **
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CY7C374
Switching Characteristics Over the Operating Range[10]
7C374-100 Parameter Combinatorial Mode Parameters tPD tPDL tPDLL tEA tER tWL tWH tIS tIH tICO tICOL Input to Combinatorial Output Input to Output Through Transparent Input or Output Latch Input to Output Through Transparent Input and Output Latches Input to Output Enable Input to Output Disable Clock or Latch Enable Input LOW Time[5] Clock or Latch Enable Input HIGH Time Input Register or Latch Set-Up Time Input Register or Latch Hold Time Input Register Clock or Latch Enable to Combinatorial Output Input Register Clock or Latch Enable to Output Through Transparent Output Latch
[5]
7C374-83
7C374-66 7C374L-66 Unit
Description
Min. Max. Min. Max. Min. Max.
12 15 16 16 16 3 3 2 2 16 18 4 4 3 3
15 18 19 19 19 5 5 4 4 19 21
20 22 24 24 24
ns ns ns ns ns ns ns ns ns
Input Registered/Latched Mode Parameters
24 26
ns ns
Output Registered/Latched Mode Parameters tCO tS tH tCO2 tSCS tSL tHL fMAX1 fMAX2 fMAX3 tOH-tIH 37x Clock or Latch Enable to Output Set-Up Time from Input to Clock or Latch Enable Register or Latch Data Hold Time Output Clock or Latch Enable to Output Delay (Through Memory Array) Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) Set-Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable Maximum Frequency with Internal Feedback (Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[5] Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO) Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH)) Output Data Stable from Output clock Minus Input Register Hold Time for 7C37x[5, 11] 10 12 0 100 143 76.9 0 6 0 16 12 15 0 83 125 67.5 0 7 8 0 19 15 20 0 66 100 50 0 8 10 0 24 10 ns ns ns ns ns ns ns MHz MHz MHz ns
Pipelined Mode Parameters tICS fMAX4 Input Register Clock to Output Register Clock Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) 10 100 12 83.3 15 66.6 ns MHz
Document #: 38-03021 Rev. **
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CY7C374
Switching Characteristics Over the Operating Range[10] (continued)
7C374-100 Parameter Reset/Preset Parameters tRW tRR tRO tPW tPR tPO Asynchronous Reset Width[5] Asynchronous Reset Recovery Time[5] Asynchronous Reset to Output Asynchronous Preset Width
[5]
7C374-83
7C374-66 7C374L-66 Unit
Description
Min. Max. Min. Max. Min. Max.
12 14 18 12 14 18
15 17 21 15 17 21
20 22 26 20 22 26
ns ns ns ns ns ns
Asynchronous Preset Recovery Time[5] Asynchronous Preset to Output
Notes: 10. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 11. This specification is intended to guarantee interface compatibility of the other members of the CY7C370 family with the CY7C374. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.
Document #: 38-03021 Rev. **
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CY7C374
Switching Waveforms
Combinatorial Output
INPUT tPD COMBINATORIAL OUTPUT
7C374-7
Registered Input
REGISTERED INPUT tIS INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tIH
tWH CLOCK
tWL
7C374-8
Registered Output
INPUT tS CLOCK tCO REGISTERED OUTPUT tWH CLOCK
7C374-9
tH
tWL
Document #: 38-03021 Rev. **
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CY7C374
Switching Waveforms (continued)
Latched Output
INPUT tS LATCH ENABLE tPDL LATCHED OUTPUT
7C374-10
tH
tCO
Latched Input and Output
LATCHED INPUT
tPDLL LATCHED OUTPUT tICOL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tSL tHL
Clock to Clock
REGISTERED INPUT
INPUT REGISTER CLOCK tICS UTPUT REGISTER CLOCK
7C374-12
tSCS
Document #: 38-03021 Rev. **
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CY7C374
Switching Waveforms (continued)
Latched Input
LATCHED INPUT tIS LATCH ENABLE tPDL COMBINATORIAL OUTPUT tICO tIH
tWH LATCH ENABLE
tWL
7C374-13
Asynchronous Reset
tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK
7C374-14
Asynchronous Preset
tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK
7C374-15
Document #: 38-03021 Rev. **
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CY7C374
Switching Waveforms (continued)
Output Enable/Disable
INPUT tER OUTPUTS
7C374-17
tEA
Ordering Information
Speed (MHz) 100 Ordering Code CY7C374-100AC CY7C374-100GC CY7C374-100JC 83 CY7C374-83AC CY7C374-83GC CY7C374-83JC CY7C374-83AI CY7C374-83JI CY7C374-83GMB CY7C374-83YMB 66 CY7C374-66AC CY7C374-66GC CY7C374-66JC CY7C374-66AI CY7C374-66JI CY7C374-66GMB CY7C374-66YMB CY7C374L-66AC CY7C374L-66JC Package Name A100 G84 J83 A100 G84 J83 A100 J83 G84 Y84 A100 G84 J83 A100 J83 G84 Y84 A100 J83 Package Type 100-Pin Thin Quad Flat Pack 84-Pin Grid Array (Cavity Up) 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Pin Grid Array (Cavity Up) 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 84-Pin Grid Array (Cavity Up) 84-Pin Ceramic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Pin Grid Array (Cavity Up) 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 84-Pin Grid Array (Cavity Up) 84-Pin Ceramic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier Commercial Military Industrial Commercial Military Industrial Commercial Operating Range Commercial
Document #: 38-03021 Rev. **
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CY7C374
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC1 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameter tPD tPDL tPDLL tCO tICO tICOL tS tSL tH tHL tIS tIH tICS tEA tER Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
UltraLogic and FLASH370 are trademarks of Cypress Semiconductor Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation. ABEL is a trademark of Data I/O Corporation. CUPL is a trademark of Logical Devices Incorporated. LOG/iC is a trademark of Isdata Corporation.
Document #: 38-03021 Rev. **
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CY7C374
Package Diagrams 100-Pin Thin Quad Flat Pack A100
Document #: 38-03021 Rev. **
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CY7C374
Package Diagrams (continued)
84-Pin Grid Array (Cavity Up) G84
51-80015-A
84-Lead Plastic Leaded Chip Carrier J83
Document #: 38-03021 Rev. **
Page 14 of 16
CY7C374
Package Diagrams (continued) 84-pin Ceramic Leaded Chip Carrier Y84
Document #: 38-03021 Rev. **
Page 15 of 16
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C374
Document Title: CY7C374 UltraLogicTM 128-Macrocell Flash CPLD Document Number: 38-03021 REV. ** ECN NO. 106324 Issue Date 05/08/01 Orig. of Change SZV Description of Change Transferred from Spec number: 38-00214 to 38-03021.
Document #: 38-03021 Rev. **
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